This invention relates to a process for forming a Schottky barrier gate on a Gallium-Arsenide (GaAs) substrate and more particularly to a method for forming such a gate using a lift-off process in conjunction with a clear field mask and metal transfer layer.
GaAs is widely used in digital and analog integrated circuits and particularly in metal-semiconductor field effect transistors (MESFET). In forming a MESFET, the metal Schottky barrier gate, typically less than a micron in length and up to a few hundred microns in width, must be precisely deposited to achieve the speed desired. The present invention focuses on a novel lithographic lift-off, etching, and metal deposition process which precisely forms the Schottky barrier gate.
Considered in more detail, a concise description of the fabrication of a MESFET may be found in "GaAs Digital IC Processing--A Manufacturing Perspective", by A. Rode and J. Roper, Solid State Technology, February, 1985, pp. 209-215. Another article in the same issue, "Manufacturing Technology for GaAs Monolithic Microwave Integrated Circuits", pp. 199-205, by T. Andrade, also provides background information related to known processing techniques.
In a typical known method for producing a digital integrated circuit such as a MESFET, a GaAs substrate is appropriately doped to form an active layer and source and drain regions. The substrate is then capped with an insulator, e.g. SiO.sub.2, and annealed to activate the doped layers electrically. The insulator is then removed, and the substrate is coated with a passivating dielectric material, e.g. such as silicon nitride, which can also be used as a lift-off agent for subsequent metallizations. Contact regions are then formed on the source and drain regions using a lift-off process, and the contact regions are annealed to form ohmic contacts. Gate metallization is then performed, which can also be performed with a masking and lift-off process, and the gate metal is recessed into the GaAs to provide appropriate threshold or pinchoff voltages. A first level metallization is then performed, followed by a second level metallization, such as an airbridge, to provide electrical connection between lines with a minimum of parasitic capacitance.
Numerous lift-off processes have been used in the past for IC processing, such as that described by P. Grabbe, et al., in "Tri-Level Lift-Off Process for Refractory Metals" in the Journal of Vacuum Science & Technology, May-June, 1982, pp. 33-34. Another approach is described by A. Milgram, in "Lift-Off Process for Achieving Fine-Line Metallization", published in the Journal of Vacuum Science & Technology, Apr.-Jun., 1983, pp. 490-493. Background information is also provided by E. L. Hu, et al., in "METAL-ON-POLYMER MASKS FOR ION BEAM PROCESSING", a paper presented at the Tenth International Conference on Electron and Ion Beam Science & Techhnology, held in Montreal, Canada in May, 1982.